This invention relates generally to analog and digital electronics, and more particularly to an improved sample and hold circuit.
The bandwidth and settling time of a sample and hold stage of a switched capacitor circuit is a function of the closed looped gain in an operational amplifier utilized in the stage. To sample and track an analog input, a unity gain is needed across the operational amplifier. This requirement places the operational amplifier at a unity gain operating point. For a single pole system, the bandwidth and settling time of a sample and hold stage are functions of the transconductance of the operational amplifier divided by the total output load capacitance.
To increase the speed at which the sample and hold stage can sample and track the analog input, conventional sample and hold stages increase the transconductance of the operational amplifier. One means of increasing the transconductance of the operational amplifier is by increasing the internal bias current of the input devices inside the operational amplifier. However, such a technique also undesirably increases the power dissipation of the sample and hold stage and reduces the bias swing of transistors within the input stage of the operational amplifier. Such technique also decreases the output impedance of devices within the operational amplifier with the negative effect of reducing the open loop gain of the operational amplifier. A second alternative means of increasing the transconductance of the operational amplifier involves increasing the aspect ratio of devices, such as transistors, inside the input stage of the operational amplifier. However, this second technique also undesirably increases the input capacitance of the operational amplifier, thereby worsening feedback caused by parasitic capacitances. Thus, both of these alternatives do not achieve improving the bandwidth or response time of sample and hold stages of switched capacitor circuits without either increasing power dissipation or the input capacitance of the operational amplifier.
As data converters such as analog to digital converters and digital to analog converters are used increasingly in high-speed data transfer applications, in many cases, the bandwidth and settling time of the sample and hold stage in a switched capacitor circuit is the principal bottleneck in time critical applications. Such switched capacitor circuits are also used significantly in filters designed for high-speed applications. Again, the bandwidth and settling time of the sample and hold stage in switched capacitor circuits in such filters becomes a bottleneck within such high-speed applications.
In accordance with the present invention, an improved sample and hold circuit is provided that substantially eliminates or reduces disadvantages and problems associated with previously developed systems and methods.
In one embodiment of the present invention, a sample and hold circuit is disclosed that includes an operational amplifier, the operational amplifier having a first and a second input and an output. The sample and hold circuit also includes a first feedback path of the operational amplifier, the first feedback path including a first capacitor coupled to the first input of the operational amplifier and a first switch coupled to the output of the operational amplifier. The sample and hold circuit further includes a second feedback path including a second capacitor coupled to the first input of the operational amplifier and a second switch coupled to the output of the operational amplifier. The sample and hold circuit additionally includes a third capacitor coupled to the first input of the operational amplifier.
In a second embodiment, a sample and hold circuit is disclosed that includes an operational amplifier and a plurality of switched capacitors, the switched capacitors introducing a closed loop gain of one-half for the operational amplifier.
Technical advantages of the present invention include presenting an improved sample and hold circuit addressing disadvantages of previous systems and methods. In particular, various embodiments of the present invention increase the bandwidth of a sample and hold circuit without increasing the input parasitic capacitance of the operational amplifier used in such sample and hold circuit. Additionally, various embodiments of the present invention improve the speed at which analog inputs may be sampled and held without dissipating additional power in the operational amplifier of such sample and hold circuit. A further advantage of various embodiments of the present invention is that a sample and hold circuit is presented that allows an increased bandwidth for such sample and hold circuit without substantial degradation of the opened loop gain of the operational amplifier or the bias swing of devices inside the operational amplifier. Yet another advantage of the present invention is that a sample and hold circuit is presented that may be used in a switched capacitor circuit where the settling time required is less than a few nanoseconds and where minimal parasitic capacitors are required.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions and claims.